Aspects of the present invention relate generally to the field of integrated circuit design, and more specifically to self-alignment of features in the “Pad” mask. The Pad mask is used in the process of positive tone self-aligned double patterning (SADP). There are 3 masks involved in this method of Double Patterning Technology (DPT): 1) The core or mandrel mask, 2) The trim mask, and 3) the Pad mask. Positive tone SADP is where the spacer becomes the drawn feature and therefore limits drawn features to the single spacer size. Any features drawn wider than a spacer are placed on the Pad mask.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, as the shapes and the spaces between shapes being patterned are often smaller than 40 nm, the ability to transfer an accurate design involving small and closely spaced components onto the substrate is limited by the physical constraints of the photolithography process.
For example, when very small shapes are included as part of the design, alignment is critical. Small misalignments of the shapes etched into the substrate may result in misconnections, feature breaks, and shorts. Alignment is particularly difficult for features that are transferred to the substrate using separate masks in a double or multi-patterning technology. For example, small closely packed features, each having a width less than 40 nm or spaced within 40 nm of each other, may conventionally be patterned with a first mask and larger features may be subsequently patterned with a second mask. Therefore, exact alignment of features on the first mask with the features on the second mask is difficult and often problematic.
Accordingly, there is a need in the art to ensure proper alignment of features patterned on a semiconductor substrate using multiple masks.